1. Field of the Invention
This invention relates to an address generating method and circuit for generating addresses of a buffer memory used when converting the scanning direction of image data, particularly addresses of a memory which stores two-dimensionally arrayed data.
2. Description of the Prior Art
Recent progress in semiconductor technology has made it possible to process two-dimensional image data, which is generated at high speed and in large quantities, in the form of a digital signal on a real-time basis.
Since image data contains a very large amount of information, preserving the data in its present form necessitates a memory having an enormous capacity. Accordingly, data-compression processing is often executed in order to economize on the amount of memory used.
One example of data-compression processing which recently has become the center of much attention is referred to as a discrete cosine transformation. This is a modification of a discrete Fourier transformation and requires that a matrix operation be performed twice to transform one block. It is possible for such a matrix operation to be executed in real-time by using an LSI referred to as the "A121" (manufactured by SGS-Tomson), by way of example.
In accordance with such a transformation, if data prior to the transformation is data in real space, then the data after the transformation will be data in frequency space (or more precisely, data in space approximating frequency space). Accordingly, in order to return the transformed data to the original data in real space, a reverse-discrete cosine transformation is required to be executed. This reverse transformation also is executed twice, and such execution is possible with the "A121" LSI mentioned above.
It should be noted that merely executing the discrete cosine transformation and reverse transformation described thus far does not result in any data compression whatsoever. In order to perform data compression, it is necessary to apply re-quantization or the like to the data, in frequency space, resulting from the discrete cosine transformation.
Furthermore, if data compression is to be performed to a greater degree, the re-quantized data in frequency space must be arrayed in ascending order in terms of frequency, and Huffman coding (one type of variable-length coding) must be carried out.
The JPEG (Joint Photographic Expert Group) has set up standards regarding methods of data compression.
The present invention concerns means by which data in frequency space can be arrayed in ascending order in terms of frequency.
The "ascending order of frequency in frequency space having a two-dimensional spread" referred to here is the order of the kind shown in FIG. 6. Ordinarily, the scanning of data in this fashion is referred to as "zigzag" scanning.
In the prior art, the rearrangement of data (hereinafter referred to as "scan conversion") is carried by a configuration of the kind shown in FIG. 7. The scan conversion operation will now be described with reference to FIG. 7.
Ordinarily, data cut into a square shape is scanned through a sequence of the kind shown in FIG. 8(a) or (b) to perform a data transfer. Further, an input/output sequence of data in a discrete cosine transformation LSI described above is similar to this sequence. The data thus scanned is inputted through an input terminal 306 shown in FIG. 7 and written in a memory 305.
The address information of the memory 305 which stores this data is generated by a counter 301 and applied to the memory 305 via a selector 303. If the scanning sequence of the input data is made that of FIG. 8(a) and the image size is limited to 8.times.8 pixels, the storage addresses of the data will have the values shown in FIG. 9. In order to read the stored data through the zigzag scanning sequence shown in FIG. 6, the corresponding addresses must be applied to the memory.
More specifically, in order to generate addresses, it is required that the output of the decoder 301 be decoded or that these addresses be read out of a memory in the order in which they were generated. However, with a data size of 8.times.8 pixels, the addresses are 64 values and therefore a decoder circuit of very large scale is required. Accordingly, the usual practice is to adopt the latter method, namely the arrangement using the memory in which the zigzag scanning addresses have been stored in the order in which they were generated. This memory is a ROM (read-only memory) 701 shown in FIG. 7. At this time the ROM 701 is selected by the selector 303 so that the addresses are applied to the memory 305.
By virtue of the above-described arrangement, the data that has been written in the memory 305 is read out in the zigzag scanning sequence based upon the address information generated by the ROM 701 via the selector 303, and this data is outputted to an output terminal 307.
Furthermore, an address signal for reading the address information out of the ROM 701 in order is supplied by the counter 301.
However, in the case where the two-dimensionally arrayed data transferred by the ordinary scanning method is scanned and transformed in zigzag fashion according to the example of the prior art described above, a memory for address conversion is required, the number of component parts increases and cost is raised.